India Bets $655M on Its First 3D AI Chip Packaging Plant

By Priya Raman

A ₹6,200 crore ($655 million) Memorandum of Understanding signed at the Madhya Pradesh Semiconductor Summit 2026 commits a company incorporated eight months ago to building India's first facility for 2.5D/3D advanced chip packaging. The promise is concrete. The evidence base is not yet.

What does the deal actually contain?

Paras Semiconductors, a subsidiary 70% owned by Paras Defence and Space Technologies, signed the MoU with the Madhya Pradesh State Electronics Development Corporation. The greenfield facility is slated for 50 acres in the Indore–Ujjain corridor. Chief Minister Dr. Mohan Yadav inaugurated the two-day summit at the Brilliant Convention Centre in Indore, which runs through October 24.

The target process category matters more than the headline number. The facility is designed for 3D heterogeneous integration and 2.5D/3D advanced IC packaging — the category TSMC's CoWoS (Chip on Wafer on Substrate) process occupies, and which every NVIDIA and AMD AI accelerator on the market depends on. India's three operational OSAT plants (outsourced semiconductor assembly and test) in Sanand, Gujarat — run by Micron, Kaynes Semicon, and CG Power — all use legacy wire-bonding processes.

The summit's total projected investment reached ₹15,800 crore (approximately $1.67 billion): five projects already granted land totaling ₹10,000 crore ($1.06 billion), plus five proposals worth ₹5,800 crore ($613 million) under review. More than 50 companies are exhibiting.

Why is advanced packaging different?

Legacy packaging places each die in a package, bonds it with thin gold, aluminum, or copper wires, and encapsulates it in epoxy. That produces QFN, BGA, and SOIC chips for automotive sensors and consumer electronics. It cannot serve an AI accelerator.

An NVIDIA H100 or AMD MI300X must move terabytes per second between logic dies and memory. Wire bonding physically cannot support that bandwidth. 2.5D packaging solves this with an interposer — a thin slab of silicon, glass, or organic material carrying metal wiring finer than any circuit board — on which the GPU die and four to eight stacks of High-Bandwidth Memory sit side by side, connected through thousands of Through-Silicon Vias (tiny metal-filled channels through the silicon). 3D packaging stacks dies vertically; AMD's 3D V-Cache is a commercial example.

What is missing from the announcement?

Two gaps stand out. First, ISM 2.0, India's national incentive program, requires advanced packaging applicants to already own or license production-grade technology for their proposed process. Paras Semiconductors has not disclosed any technology partner. Tata Electronics partnered with PSMC of Taiwan for its Dholera fab; CG Power partnered with Renesas. No comparable name has appeared here. Without one, the path to the 35% capex support reserved for 2.5D/3D projects — versus 25% for legacy OSAT — remains unconfirmed.

Second, the equipment. Die-to-wafer bonding, thermal compression bonding, interposer lithography, and advanced underfill chemistry would all need importing, just as the Sanand plants import their equipment.

The parent company's rationale is at least explicit. Paras Defence, founded in 1996 and listed on the NSE and BSE, built its business on optics, optronics, tactical communications, and missile and naval components. Its precision-engineering and cleanroom experience overlaps with assembly operations. The facility will initially serve sensor technologies, optical systems, and strategic sectors.

CEO Santosh Kumar said at the MoU signing that "the next phase of India's semiconductor growth would depend on building strong manufacturing ecosystems." Managing Director Munjal Sharad Shah called the project a milestone in indigenous capability. Neither statement addressed the licensing question.

Why Madhya Pradesh?

Gujarat clustered its first wave around Sanand. Madhya Pradesh argues interior India's cheaper land and the Indore–Ujjain corridor can win the second cluster. The state approved its Semiconductor Policy 2025 in February 2025 — before ISM 2.0's July 2026 approval — allowing incentives to stack. State incentives include:

• Capital subsidy up to 25% of project cost (or 50% of the central subsidy), or 40% for non-centrally approved projects, capped at ₹150 crore ($15.9 million)
• 6% annual interest subsidy for five years, capped near ₹10 crore
• Concessional land rates
• ₹2 per unit (about $0.02/kWh) power tariff subsidy for ten years

Can India reach the 2035 target?

NITI Aayog's Frontier Tech Hub roadmap, released May 2026, names advanced packaging as India's clearest near-term opportunity to become a top-three global OSAT destination by 2035. The global advanced packaging market stood at $20.2 billion in 2024 and is projected at $39.6 billion by 2030, per Grand View Research.

India's semiconductor effort now runs in three chapters: legacy OSAT is operational in Sanand; advanced packaging has commitments but no facility; leading-edge fabrication has one project, Tata's Dholera fab targeting first silicon at 90nm in mid-2028. Business Today's September 2026 analysis put the constraint plainly: advanced packaging offers "a faster route to commercial semiconductor relevance" but not "a shortcut to semiconductor power," citing thin local ecosystems for substrates, materials, equipment, and experienced packaging engineers.

The gap between a ₹6,200 crore announcement and an operating 2.5D line closes through construction, licensing, and customers — not through summits. As of October 23, Paras has demonstrated only the first.