GPU memory could leap from current 80–192 GB HBM stacks to multiple terabytes under a new storage-inspired architecture, according to The Register.

The outlet's headline — "GPUs could explode to multiple TB with new storage-inspired memory tech" — points to a research direction that would alter on-device GPU memory hierarchies. The piece, published on The Register's site, does not yet disclose vendor, schedule, or substrate details in its headline summary.

What is driving the search for multi-TB GPU memory

Today's top-end accelerators rely on High Bandwidth Memory (HBM) stacks. Nvidia's H100 ships with 80 GB of HBM3, the H200 reaches 141 GB of HBM3e, and the B200 delivers 192 GB of HBM3e. Eight-way HGX baseboards multiply those figures, but per-device ceilings still bind large-model training and inference.

A multi-TB GPU would change that math. Such a device could host parameter sets locally, removing sharding overhead that today routes activations across NVLink-connected groups of accelerators.

What does "storage-inspired" imply

Storage-class memory research has produced several candidates over the years. Intel and Micron's 3D XPoint effort, marketed as Optane, has ended. MRAM, ReRAM, and NAND-derived computational storage devices continue to advance in foundries and labs worldwide. The Register's headline does not identify which substrate the GPU work uses.

Each candidate carries distinct trade-offs. NAND scales cheaply per gigabyte but incurs microsecond-class latency and limited write endurance. MRAM and ReRAM close the latency gap while improving density over SRAM, but cost more per bit and face manufacturing-scale hurdles.

Why HBM economics matter

HBM economics already constrain scaling. An HBM3e stack runs several hundred dollars at current spot rates, and an 8-GPU baseboard consumes eight of them. A storage-class alternative could reduce per-gigabyte cost substantially, though any GPU tier built from it would still compete with planned HBM4e pricing.

What questions does the headline leave open

• Latency versus HBM3e and HBM4: multi-TB capacity delivers no benefit if every fetch costs microseconds.
• Bandwidth per stack: HBM supplies TB/s-class throughput, hard to match outside DRAM.
• Endurance: training workloads rewrite memory aggressively.
• Manufacturing path: fab-ready processes or entirely new production lines.
• Software stack: CUDA, ROCm, and Triton compilers are tuned for HBM, not storage-class latency profiles.

Why does the timing matter

The HBM roadmap runs through 2027 with HBM4 and HBM4e. Per-stack capacities exceed 36 GB, and aggregate bandwidth targets reach 1.5 TB/s. A multi-TB GPU built on storage-class memory would complement HBM rather than replace it, sitting below registers and above DRAM-attached expansion pools.

What would a working multi-TB GPU change

Inference economics shift for long-context models. Mixture-of-experts routing, KV-cache sizing for million-token windows, and on-device retrieval-augmented generation all benefit from larger memory pools. Training could see similar gains by reducing inter-GPU all-reduce traffic across NVLink and InfiniBand fabrics.

The Register has not yet named the research group, lab, or vendor behind the technology. Follow-up coverage is expected as the underlying research surfaces.