Pat Gelsinger, Intel's former CEO, has called HBM a "hideous memory" — a blunt verdict from the man who ran the company that spent years deciding whether to compete in the high-bandwidth memory market at all. He didn't stop at the label, either. Gelsinger's critique, as reported by Wccftech, centers on three technical shortcomings: terrible bit density, thermal problems, and what he describes as shoreline bandwidth issues.

What does Gelsinger's critique actually target?

HBM stacks DRAM dies vertically and places them right next to the compute die, which is why it's become the default memory for AI accelerators. But Gelsinger's argument cuts at the economics and physics of that arrangement.

The complaints he lists map onto known engineering trade-offs:

• Bit density — HBM delivers less capacity per wafer than conventional DRAM, making it an expensive way to buy memory.
• Thermals — stacked dies packed against a hot GPU complicate cooling budgets.
• Shoreline bandwidth — the interconnect approach constrains how much bandwidth you can actually extract along the edge of the die.

For practitioners, the significance is less the technical argument than the source. Gelsinger ran Intel during the exact period when HBM demand exploded alongside AI accelerators, and his framing suggests he never bought the industry consensus that HBM is the only viable path for high-bandwidth workloads.

It's also worth remembering that Intel under Gelsinger pursued its own packaging-heavy strategy, leaning on approaches like EMIB and Foveros rather than following the HBM-centric playbook of Nvidia and AMD. His comments read as a continuation of that argument, now made from outside the company.

Where does the supply side stand?

While Gelsinger was dismissing the technology, Nanya was reiterating something more consequential for buyers: DRAM shortages will persist until 2028. That's a three-year horizon of tight supply, and it comes from a major memory maker rather than an analyst forecast.

For anyone procuring memory — whether standard DRAM for servers or capacity constrained by the AI-driven HBM buildout — the two messages combine uncomfortably. The industry's preferred high-bandwidth solution has, in Gelsinger's view, fundamental architectural flaws, and the conventional alternatives will be scarce for roughly the next three years.

The shortage projection isn't new from Nanya, hence the word "reiterates." The company has been signaling extended tightness in the DRAM market as AI demand absorbs capacity that once served conventional computing. What's changed is the confidence: 2028 is now the stated endpoint, not a vague "next few years."

Why does the disagreement matter?

You have the former head of the world's most advanced logic manufacturer calling the industry's flagship AI memory "hideous," while one of its suppliers says there won't be enough conventional DRAM to go around for three years. Those positions aren't contradictory — you can believe HBM is inefficient and still accept that everyone will keep buying it — but together they frame the industry's current bind.

For engineers and architects, Gelsinger's critique invites a harder look at alternatives: nearer-memory compute, different packaging schemes, or memory technologies that don't carry HBM's density and thermal penalties. For procurement teams, the Nanya timeline means planning around scarcity through at least 2027, with 2028 as the earliest relief.

Neither Intel nor Nanya has responded further to Gelsinger's remarks. The comments stand as one of the sharpest public criticisms of HBM from a executive of his seniority — and they arrive while the memory market can least afford a technology debate.