Test report DSG-6738 · Rev A · tested October 10, 2026

Memory & StorageDevice under test

CXMT commits 18 billion yuan to DRAM R&D and testing capacity

CXMT will invest 18 billion yuan in DRAM research, development, and testing capacity according to the Global Times, reinforcing China's domestic memory program outside the Korean and Taiwanese incumbents.

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Spec summary

  1. CXMT will allocate 18 billion yuan to DRAM R&D and testing capacity
  2. The funding covers process development and qualification infrastructure in one envelope
  3. China's domestic memory program ranks among the largest single-vendor DRAM capex commitments outside South Korea and Taiwan
  4. Global Times did not specify a deployment timeframe, wafer output target, or process node
  5. CXMT has not published a full multi-year capital plan through standard investor disclosure
China’s CXMT to invest 18b yuan in DRAM R&D and testing capacity - Global Times
Fig. AChina’s CXMT to invest 18b yuan in DRAM R&D and testing capacity - Global Times — AI-generated

CXMT, China's main domestic DRAM developer, will allocate 18 billion yuan to research and development and to testing capacity, the Global Times reported. The investment ranks as one of the largest single-vendor DRAM capex commitments attributed to a Chinese supplier.

What the funding covers

The 18 billion yuan envelope targets two operational areas. The first funds continued process development on current and future DRAM nodes. The second scales in-house test and packaging infrastructure used to qualify finished wafers before commercial shipment.

Testing infrastructure frequently bottlenecks emerging DRAM makers. Wafer-level probing and final-test cycles gate yield ramps, and the largest merchant test houses serve the dominant global vendors first. Building proprietary test lines gives a supplier tighter control over qualification timelines and reduces exposure to third-party capacity constraints concentrated in Taiwan and South Korea, where much of the global assembly and test industry sits.

Why combine R&D and test spending

Chinese semiconductor policy has consistently paired fab construction with the surrounding test and assembly ecosystem inside one investment scope. A fab can produce wafers it cannot sell if external validation cannot be reached inside commercial timeframes. OEM qualification cycles draw statistical samples from stable, high-yield production lines — exactly the kind of statistical basis that demands dedicated, high-volume test capacity.

Packaging and test spending inside the same envelope as R&D treats the upstream and downstream halves of memory manufacturing as one program rather than two. For a vendor still climbing the yield curve, that integration shortens the path from research wafer to qualified product.

Market implications

For global DRAM pricing, 18 billion yuan is modest in absolute terms. The dominant memory suppliers run multi-billion-dollar quarterly capex programs as a baseline. The signal value of the CXMT figure sits elsewhere: it confirms that the Chinese program intends to remain in the technology race rather than settle for trailing-node commodity production.

Hyperscale procurement teams — cloud service providers and AI compute operators — track Chinese DRAM capacity because additional supply above projected demand relieves contract pricing pressure, and because a qualified second-source vendor offers geopolitical insurance against disruption in the established DRAM-producing regions.

What remains undisclosed

The Global Times headline does not specify a deployment timeframe, a wafer output target, or a process node. The 18 billion yuan figure itself may represent fresh capital, a re-announced prior commitment, or an aggregation of overlapping programs. CXMT has not published a full multi-year capital plan through standard investor disclosure channels.

For outside observers, the cleanest reading of the announcement is directional. CXMT is committing resources to stay in DRAM at scale, together with the test infrastructure required to ship commercial volumes. The exact timetable and node targets will determine how quickly that capacity translates into competitive pressure on the three-vendor concentration that has defined DRAM since the early 1990s.

via Google News: DRAM chip (Source)

Filed under

  • cxmt
  • dram
  • china-semiconductor
  • memory-manufacturing
  • dram-testing
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News editor covering marketplaces and e-commerce at Die Signal.

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