AMD holds a 46% revenue share of the X86 server CPU market in early 2026, up from roughly 0% in 2015, CEO Lisa Su said at the Advancing AI 2026 event in Silicon Valley. Su rolled out the company's Venice Epyc 9006 server CPUs, the MI455X and MI430X Instinct accelerators, and the Helios rackscale platform.

How did AMD reach 46% of X86 server share?

AMD exited the datacenter in the early 2010s after Opteron bugs and Intel's Nehalem Xeon launch collided with the Great Recession. The first Naples Epyc chips followed two years after the 2015 re-commitment.

The Turin Epyc 9005 generation, which debuted in October 2024, ships with 128 cores and 256 threads in Zen 5 variants and 192 cores and 384 threads in the Zen 5c variants. Arm-based CPUs, mostly from hyperscaler homegrown designs and Nvidia's Grace CG100 parts, now account for around half of server shipments and revenues.

What does the Venice lineup deliver?

Venice Epyc 9006 parts use TSMC's N2 process on compute dies and a 6nm process on I/O dies. The top-end Zen 6c variant carries 256 cores across eight 32-core complexes with 512 threads. Aggregate memory bandwidth reaches 1.6 TB/sec on DDR5, supported by 16 memory controllers handling 12.8 GHz MRDIMMs or 8 GHz RDIMMs on the SP7 platform.

The Zen 6c delivers a 1.8X performance-per-socket gain over Turin at like-for-like SPEC int 2006. It is the first server compute engine to support PCI-Express 6.0. The 128-core Zen 6 part targets enterprise back-office workloads on the smaller SP8 socket with eight memory channels.

The Venice HF variant packs 12 Zen 6 cores per chiplet across 8 chiplets, pushing clocks to 5 GHz for high single-threaded performance. A Venice-X version adds 3D vertical cache for cache-sensitive HPC and AI workloads. A 2027 spin-off called "Verano" swaps DDR5 for LPDDR5, mirroring Nvidia's Grace and Vera designs.

"The idea is to give agentic AI sandboxes the highest performance per rack and per watt and per dollar, bar none," Su said.

What does the MI455X bring to GPU compute?

The MI455X uses the CDNA 5 architecture on TSMC N2 and N3 processes. A dozen compute and I/O chiplets carry 320 billion transistors around the double-chiplet Altair compute complex. AMD rates the device at 20 PFLOPS FP8 and 40 PFLOPS FP4, backed by 432 GB of HBM4 across 12 controllers at 23.3 TB/sec aggregate bandwidth.

The MI430X targets HPC modeling at 288 TFLOPS FP64, 8.7X the 33 TFLOPS that Nvidia's Rubin GR200 reaches on its tensor cores. It uses the same 432 GB HBM4 and 23.3 TB/sec as the MI455X, beating Nvidia's Vera GPU by 50% in capacity and 6% in bandwidth. The MI430X ships in the first half of 2027.

What does the Helios rack look like?

The initial Helios rack pairs a 96-core Venice HF processor with four Altair MI455X GPUs linked by UALink over Ethernet. Pensando's Salina DPU handles storage and networking virtualization. Customers choose Broadcom's Thor Ultra or Pensando's Vulcano 800 Gb/sec AI NICs. A double-wide Helios configuration holds 72 MI455X GPUs and 18 Venice HF CPUs, totaling 4,600 CPU cores and 18,000 GPU compute complexes.

Su said Helios outperforms Nvidia's Vera-Rubin NVL72 rackscale system by up to 30% on tokens-per-dollar across inference runs. Using Moonshot AI's Kimi K2 Thinking model, Helios delivers about 15% better tokens-per-second-per-GPU at low interactivity, 12% at medium, and 10% at high.

What comes after Venice and MI455X?

The Epyc roadmap stays on a two-year cadence. Florence, the next generation, will use Zen 7 and Zen 7c cores and likely shift to DDR6 main memory. AMD may dual-source between TSMC's A14 and Intel's 14A process nodes.

The MI500 series moves to CDNA 6 with copper and optical links, HBM4E memory, and a "leadership GPU scale-up domain." AMD targets 2,000X the tokens-per-second-per-GPU of the MI300 series from four years ago. MI600 follows in 2028. Helios 500 introduces optical alongside copper interconnects; Helios 600 could be fully optical, though a 2028 all-optical launch looks aggressive given optical component ramp timelines.