TSMC has set a target of 120,000 wafers per month at its 2 nm process node by the end of 2026, according to a TechPowerUp report.

The capacity figure anchors the company's ramp plans for the next generation of leading-edge silicon. Reaching 120,000 wafers per month by December 2026 would require sustained production scaling across an 18-month window from initial 2 nm wafer-out.

Why the 120,000-wafer target is significant

A six-figure monthly wafer count places 2 nm production at the volume threshold that defines high-volume manufacturing at advanced geometries. Prior TSMC nodes, including N5 and N3, reached comparable monthly wafer volumes during their respective high-volume production phases, giving the foundry a reference curve for execution on the 2 nm build.

Where 2 nm sits in the process lineup

The 2 nm node is positioned as the successor to the 3 nm family. Volume production at the 120,000-wafer scale by end of 2026 would give fabless chip designers access to next-generation transistor density and power efficiency on a manufacturing footprint comparable to what 3 nm achieved at the equivalent point in its ramp.

Open questions from the report

The TechPowerUp report does not specify:

• Which TSMC fab sites will host the 120,000-wafer capacity
• Customer allocations across the 2 nm ramp
• The split between the base 2 nm process and any variant nodes
• Capital expenditure earmarked for the build-out

Those details typically surface in TSMC's quarterly earnings disclosures and at its annual technology symposium.

What the milestone means going forward

The disclosed capacity target provides chip designers, equipment suppliers, and competing foundries with a fixed planning number for the next 18 months. Actual ramp progress against the 120,000-wafer benchmark will serve as a key indicator of TSMC's execution on its leading-edge roadmap through 2026.