SK hynix and Samsung are advancing 16-layer HBM4 memory designs, while NVIDIA's Rubin GPU platform will deploy 12-layer HBM4 modules, according to The Korea Herald.

The configuration split highlights competing priorities as the industry transitions to HBM4, the fifth generation of JEDEC-standardized high-bandwidth memory. Korean suppliers are pushing denser stacks to win next-generation orders, while NVIDIA's 12-layer selection for Rubin points to a yield-and-thermals-first approach for the platform's launch.

What changes between 12-layer and 16-layer HBM4?

Each HBM stack consists of multiple DRAM dies bonded vertically through through-silicon vias (TSVs). Going from 12 to 16 layers raises the per-package capacity and the memory bandwidth ceiling. A 16-high stack built on 24 Gb dies would deliver 48 GB per package, versus 36 GB for a 12-high configuration at the same die density.

Higher layer counts also raise the bar for thermal management and die-yield requirements, because a single defective die in the stack typically forces the entire package to be scrapped. The 12-layer baseline has been in volume production since the HBM3E generation, giving suppliers a known yield curve.

Why does Rubin favor 12-layer?

Rubin succeeds the Blackwell generation and targets AI training and inference workloads at data-center scale. The Korea Herald reporting indicates NVIDIA is qualifying 12-high HBM4 stacks from its memory partners for Rubin's launch window, with priorities including:

• Thermal headroom for sustained high-bandwidth operation
• Manufacturing yield at volume
• Time-to-market over peak per-package capacity

The 12-layer configuration typically delivers 1.5 TB/s or more per stack in HBM4 implementations, leaving Rubin with aggregate memory bandwidth comparable to or higher than Blackwell despite the lower stack height.

Where does this leave SK hynix and Samsung?

Both Korean suppliers are publicly targeting 16-layer HBM4 samples. SK hynix has framed 16-high HBM4 as a 2025 milestone. Samsung has emphasized custom HBM offerings for non-NVIDIA customers, including specialized base-die designs and tailored capacity options.

The 16-layer push positions both companies for post-Rubin GPU generations, custom AI ASIC programs from hyperscalers, and HBM4E and HBM5 development. NVIDIA's Rubin decision does not foreclose 16-layer adoption in later Rubin refreshes or in competing accelerators from AMD, Intel, and custom-silicon vendors.

What does the split mean for buyers?

For data-center operators and accelerator OEMs, the layer-count split means 2025–2026 HBM4 supply will skew toward 12-high modules. Higher-density 16-high parts are expected to enter qualification in late 2025 and ramp through 2026, primarily serving non-NVIDIA AI silicon programs and follow-on NVIDIA products.

JEDEC's HBM4 specification supports up to 16-high stacks and per-pin data rates of 8 Gb/s across a 2048-bit interface per stack. The standard leaves the layer count and capacity choice to the implementation, the design freedom SK hynix and Samsung are now exercising as they race to qualify 16-layer parts against NVIDIA's 12-layer Rubin baseline.