Samsung Foundry has finished the tape-out of Tesla's next-generation AI chip, Cleanroom Technology reported.

Tape-out marks the hand-off of a finalized integrated circuit layout from the design team to the foundry for mask production. From there, Samsung will produce the photomask set and begin wafer fabrication on whichever of its process nodes handles the contract, a sequence that generally runs 12 to 16 weeks before first silicon returns for a new design at an established node.

What does the tape-out actually signal?

Completing tape-out means the chip design has cleared every internal check: design-rule verification, timing closure, DFT coverage and sign-off corners. The GDSII or OASIS database is frozen at that point. Samsung converts the database into a mask set and runs the lithography, etch, deposition and chemical-mechanical polishing steps that turn the layout into physical die.

For the foundry side, the milestone represents a contract win against the most likely rival supplier, TSMC. Re-targeting a complex AI design from one foundry's PDK and standard-cell library to another's typically consumes three to nine months of engineering, so a Samsung tape-out indicates either a design built natively on Samsung's libraries or a successful migration from a competing fab.

Why does the slot matter to Samsung?

Samsung's foundry division reports annual revenue measured in the single-digit billions and trails TSMC by a wide margin in advanced-node market share. A Tesla win delivers high-visibility volume: each Model 3, Model Y, Cybertruck and Semi carries multiple inference accelerators, and Tesla's reported cumulative deliveries exceed six million vehicles across its active product lines.

Tesla also operates a separate AI training stack, Dojo, which generates additional silicon demand that the in-vehicle accelerators do not. Combined, the automotive and data-center silicon programs make Tesla a multi-program foundry customer rather than a single-chip account.

What happens after tape-out?

The post-tape-out sequence at Samsung will follow a standard path:

• Mask-shop production of the full reticle set, roughly 3-4 weeks
• First wafer lots on the assigned node, typically 6-10 weeks
• Wafer sort, die-level test and packaging, including bumping where applicable
• Sample shipment to Tesla for A0 silicon validation
• AEC-Q100 reliability stress qualification
• IATF 16949 process qualification at the fab
• High-volume ramp into production vehicles

Full automotive qualification usually consumes 12-18 months. Engineering samples and limited pre-production lots often reach development fleets before formal qualification finishes.

What the report did not disclose

The headline does not identify the process node — 4 nm, 5 nm, 7 nm or any other geometry. It also omits the chip codename, the target slot inside Tesla's compute stack, and the wafer-per-week volume commitment. Contractual pricing was not disclosed either. Neither Samsung nor Tesla had issued a public statement at the time of the report. Readers will need confirmation from one of the two principals before any of those data points can be added to the tape-out record.