NVIDIA Cuts Rubin Memory and NVLink Specs as First Hardware Ships

NVIDIA has quietly cut the shipping specifications of its Rubin GPU, dropping HBM4 memory bandwidth to 19.2TB/second per GPU — a loss of 2.8TB/second, or roughly 11%, versus the 22TB/second the company originally promoted. The revision, posted in September to NVIDIA's product pages and architecture datasheet and first spotted by IT Home, lands as the Vera Rubin ramp hits the fourth quarter of 2026 and hyperscalers begin making the first NVL72 systems generally available.

For buyers, the changes apply to all shipping Rubin hardware from day one. So there's no old-versus-new split to navigate — but there is less memory bandwidth and less NVLink scale-up bandwidth than the spec sheets promised a year ago, offset by more scale-out networking.

What changed on the Rubin GPU itself?

The headline cut is memory bandwidth. NVIDIA originally targeted 22TB/second across 8 HBM4 stacks, running each stack at about 10.75Gbps/pin. The shipping figure is 19.2TB/second, at 9.375Gbps/pin — a net loss of 1.375Gbps per pin.

Context matters here. The official HBM4 specification calls for 8Gbps/pin, and NVIDIA's original 10.75Gbps target was well above it. Even the reduced 9.375Gbps rate stays aggressive. For comparison, AMD runs its HBM4 stacks on the MI455X at just 7.6Gbps/pin. NVIDIA hasn't said why it revised the numbers down; the working assumption is that memory controller speeds, stack speeds, or yields — likely some combination — couldn't deliver at the original rates.

NVLink scale-up bandwidth drops from 3.6TB/second to a flat 3.0TB/second per GPU, a 600GB/second or 17% reduction. NVLink is where NVIDIA works hardest to make many physical GPUs behave as one, so this cut bites in exactly the fabric it usually pushes to the limit.

Scale-out networking goes the other way: 450GB/second per GPU, up from the preliminary 400GB/second.

Everything else holds. Compute throughput stays at 50 PFLOPS NVFP4 inference and 35 PFLOPS NVFP4 training, plus 250 TOPS INT8 and 2 PFLOPS TF32. Memory capacity remains 288GB of HBM4 (8×36GB). NVIDIA hit its clock speed and capacity targets.

How does the NVL72 rack change?

The flagship Vera Rubin NVL72 — integrating Vera CPUs, BlueField-4 DPUs and 72 Rubin GPUs — absorbs the per-GPU cuts in lockstep:

• GPU memory bandwidth: 1,580TB/second → 1,400TB/second, down 180TB (11%)
• NVLink scale-up bandwidth: 260TB/second → 216TB/second, down 17%
• Scale-out networking: 28.8TB/second → 32.4TB/second bidirectional, an increase
• GPU memory: unchanged at 20.7TB HBM4

Whether an NVL72 rack can hit the same AI performance with less memory and NVLink bandwidth as originally intended seems doubtful, though the compute silicon is shipping at spec. For larger deployments that lean heavily on scale-out networking, more bandwidth is now available than NVIDIA first projected.

Where does HGX Rubin NVL8 take the biggest hit?

The 8-way systems get everything above, plus a capacity cut of their own. HBM4 memory drops from 2.3TB to a flat 2.0TB — 300GB, or 13%, gone. The original figure required each GPU to carry its full 288GB complement; 2.0TB means roughly 250GB per GPU, which needs only 7 of the GPU's 8 memory stacks.

That makes NVL8 the biggest memory bandwidth loser in the entire Rubin family: 130TB/second versus the preliminary 176TB/second, a 26% cut of about 46TB/second. Per GPU, that's 16.8TB/second across 250–252GB of memory.

Training throughput also slips on NVL8:

• NVFP4 training: 280 PFLOPS → 270 PFLOPS
• FP8 training: 140 PFLOPS → 130 PFLOPS
• NVFP4 inference: unchanged at 400 PFLOPS
• Scale-out networking: 1.6TB/second → 1.8TB/second

Both versions take the hit — the HGX Rubin NVL8 (Rubin plus x86 CPU) and the HGX Vera Rubin NVL8 (Rubin plus Vera), along with DGX systems built on the NVL8 platform. The Vera Rubin Superchip and NVL4 are similarly revised.

What does this mean for deployments?

NVIDIA has clearly reined in its ambitions to bring Rubin to market at scale. The full performance ramifications are unclear, since not all workloads hit memory or networking bottlenecks the same way — and in practice it's academic, because every Rubin that ships now carries these specs. Either way, a lot of Rubin silicon is getting deployed over the next few quarters.